Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

ABSTRACT

A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

TECHNICAL FIELD

[0001] The present invention relates generally to integrated circuits,and more specifically to synchronizing an external clock signal appliedto an integrated circuit with internal clock signals generated in theintegrated circuit in response to the external clock signal.

BACKGROUND OF THE INVENTION

[0002] In synchronous integrated circuits, the integrated circuit isclocked by an external clock signal and performs operations atpredetermined times relative the rising and falling edges of the appliedclock signal. Examples of synchronous integrated circuits includesynchronous memory devices such as synchronous dynamic random accessmemories (SDRAMs), synchronous static random access memories (SSRAMs),and packetized memories like SLDRAMs and RDRAMs, and include other typesof integrated circuits as well, such as microprocessors. The timing ofsignals external to a synchronous memory device is determined by theexternal clock signal, and operations within the memory device typicallymust be synchronized to external operations. For example, data words areplaced on a data bus of the memory device in synchronism with theexternal clock signal, and the memory device must latch these data wordsat the proper times to successfully capture each data word. In thepresent description, “external” is used to refer to signals andoperations outside of the memory device, and “internal” to refer tosignals and operations within the memory device. Moreover, although thepresent description is directed to synchronous memory devices, theprinciples described herein are equally applicable to other types ofsynchronous integrated circuits.

[0003] To synchronize external and internal clock signals in modernsynchronous memory devices, a number of different clock synchronizationcircuits have been considered and utilized, including delay-locked loops(DLLs), phased-locked loops (PLLs), and synchronous mirror delays(SMDs), as will be appreciated by those skilled in the art. FIG. 1 is afunctional block diagram illustrating a conventional delay-locked loop100 including a variable delay line 102 that receives a clock buffersignal CLKBUF and generates a delayed clock signal CLKDEL in response tothe clock buffer signal. The variable delay line 102 controls a variabledelay VD of the CLKDEL signal relative to the CLKBUF signal in responseto a delay adjustment signal DADJ. A feedback delay line 104 generates afeedback clock signal CLKFB in response to the CLKDEL signal, thefeedback clock signal having a model delay D1+D2 relative to the CLKDELsignal. The D1 component of the model delay D1+D2 corresponds to a delayintroduced by an input buffer 106 that generates the CLKBUF signal inresponse to an external clock signal CLK, while the D2 component of themodel delay corresponds to a delay introduced by an output buffer 108that generates a synchronized clock signal CLKSYNC in response to theCLKDEL signal. Although the input buffer 106 and output buffer 108 areillustrated as single components, each represents all components and theassociated delays between the input and output of the delay-locked loop100. The input buffer 106 thus represents the delay D1 of all componentsbetween an input that receives the CLK signal and the input to thevariable delay line 102, and the output buffer 108 represents the delayD2 of all components between the output of the variable delay line andan output at which the CLKSYNC signal is developed.

[0004] The delay-locked loop 100 further includes a phase detector 110that receives the CLKFB and CLKBUF signals and generates a delay controlsignal DCONT having a value indicating the phase difference between theCLKBUF and CLKFB signals. One implementation of a phase detector isdescribed in U.S. Pat. No. 5,946,244 to Manning (Manning), which isassigned to the assignee of the present patent application and which isincorporated herein by reference. A delay controller 112 generates theDADJ signal in response to the DCONT signal from the phase detector 110,and applies the DADJ signal to the variable delay line 102 to adjust thevariable delay VD. The phase detector 110 and delay controller 112operate in combination to adjust the variable delay VD of the variabledelay line 102 as a function of the detected phase between the CLKBUFand CLKFB signals.

[0005] In operation, the phase detector 110 detects the phase differencebetween the CLKBUF and CLKFB signals, and the phase detector and delaycontroller 112 operate in combination to adjust the variable delay VD ofthe CLKDEL signal until the phase difference between the CLKBUF andCLKFB signals is approximately zero. More specifically, as the variabledelay VD of the CLKDEL signal is adjusted the phase of the CLKFB signalfrom the feedback delay line 104 is adjusted accordingly until the CLKFBsignal has approximately the same phase as the CLKBUF signal. When thedelay-locked loop 100 has adjusted the variable delay VD to a valuecausing the phase shift between the CLKBUF and CLKFB signals to equalapproximately zero, the delay-locked loop is said to be “locked.” Whenthe delay-locked loop 100 is locked, the CLK and CLKSYNC signals aresynchronized as long as the feedback delay line 104 accurately modelsthe delays D1, D2 of the input and output buffers 106, 108, as will bediscussed in more detail below. This is true because when the phaseshift between the CLKBUF and CLKFB signals is approximately zero (i.e.,the delay-locked loop 100 is locked), the variable delay VD has a valueof NTCK−(D1+D2) as indicated in FIG. 1, where N is an integer and TCK isthe period of the CLK signal. When VD equals NTCK−(D1+D2), the totaldelay of the CLK signal through the input buffer 106, variable delayline 102, and output buffer 108 is D1+NTCK−(D1+D2)+D2, which equalsNTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLKsignal and the two signals are synchronized since the delay is aninteger multiple of the period of the CLK signal. Referring back to thediscussion of synchronous memory devices above, the CLK signalcorresponds to the external clock signal and the CLKSYNC signalcorresponds to the internal clock signal.

[0006]FIG. 2 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop 100 of FIG. 1. Inresponse to a rising-edge of the CLK signal at a time T0, the CLKBUFsignal goes high the delay D1 later at a time T1. Initially, thevariable delay VD as a value VD1, causing the CLKDEL signal to go highat a time T3 and the CLKSYNC signal to go high at a time T4. At thispoint, note that the positive-edge of the CLKSYNC signal at the time T4is not synchronized with the CLK signal, which transitions high at atime T5. In response to the rising-edge of the CLKDEL signal at the timeT3, the CLKFB goes high at a time T6, which occurs before apositive-edge of the CLKBUF signal occurring at a time T7. Thus, thepositive-edge of the CLKFB signal occurs at the time T6 while thepositive-edge of the CLKBUF occurs at the time T7, indicating there is aphase shift between the two signals. The phase detector 110 (FIG. 1)detects this phase difference, and generates the DCONT signal just afterthe time T7 at a time T8 which, in turn, causes the delay controller 112(FIG. 1) to generate the DADJ signal to adjust the value of the variabledelay VD to a new value VD2 and thereby synchronize the CLK and CLKSYNCsignals, as depicted at a time T9. At this point, note that the variabledelay VD results in an approximately zero phase difference between theCLKBUF and CLKFB signals, as indicated at a time T10.

[0007] From this description of the conventional delay-locked loop 100,it is seen that in order for the CLK and CLKSYNC signals to beaccurately synchronized, the feedback delay line 104 must accuratelymodel the delay D1 of the input buffer 106 and delay D2 of the outputbuffer 108. For example, if the delay D2 of the output buffer 108 has avalue D2′ instead of D2, the delay-locked loop 100 will be locked (i.e.,phase difference between CLKBUF and CLKFB equals zero), but the CLK andCLKSYNC signals will not be synchronized, as illustrated at a time T11in FIG. 2. In a conventional double-data rate (DDR) synchronous dynamicrandom access memory (SDRAM), such a situation may arise when datadrivers in the memory device change from a full-drive operating mode toa reduced-drive operating mode, as will now be described in more detail.Although the principles described herein are discussed with reference toa DDR SDRAM, the principles are applicable to any memory device that mayinclude a clock synchronization circuit for synchronizing internal andexternal signals, such as conventional synchronous DRAMs (SDRAMs), aswell as packetized memory devices like SLDRAMs and RDRAMs, and areequally applicable to any integrated circuit that must synchronizeinternal and external clocking signals.

[0008] Referring back to FIG. 1, in a conventional DDR SDRAM the outputbuffer 108 corresponds to a data driver that receives a data signal DQand outputs the data signal in response to being clocked by the CLKDELsignal. In this way, as long as the delay D2 of the output buffer 108 isaccurately modeled by the feedback delay line 104, the output bufferoutputs the DQ signal on a data bus of the DDR SDRAM in synchronism withthe CLK signal. In conventional DDR SDRAMs, however, the output buffer108 operates in either a full-drive mode or a reduced-drive mode, andthe delay D2 of the output buffer can vary between modes. Morespecifically, in a conventional DDR SDRAM an extended load mode registerincludes an output drive strength bit that determines whether the outputbuffer 108 operates in the full-drive or reduced-drive mode ofoperation. A memory controller typically sets the output drive strengthbit in the extended load mode register via a load mode register commandto thereby place the output buffer 108 in the desired operating mode.The output buffer 108 is typically placed in the full-drive mode whenthe DDR SDRAM is being utilized in a conventional application, such ason a conventional memory module, while the output buffer may be placedin the reduced-drive mode when the DDR SDRAM is being utilized in apoint-to-point application such as on a graphics card, as will beappreciated by those skilled in the art. During the full-drive mode, theoutput buffer 108 provides sufficient current to drive the DQ signals tofull-range voltages for a particular loading of the data bus, whileduring the reduced-drive mode the buffer provides a reduced current todrive the DQ signals to reduced voltages given the same loading of thedata bus, as will also be appreciated by those skilled in the art.

[0009]FIG. 3 is a signal timing diagram that illustrates the operationof the output buffer 108 in the full-drive and reduced-drive modes ofoperation. In the example of FIG. 3, the CLKDEL signal goes high at atime T0, which occurs the delay D2 before the CLK signal goes high at atime T1. Three signal diagrams 300-304 below the CLK and CLKDEL signalsillustrate the three possible scenarios for the operation of the outputbuffer 108 in outputting the DQ signal when switching between thefull-drive and reduced-drive mode of operation. In the first diagram300, the output buffer 108 has substantially the same delay D2 in boththe full-drive and reduced-drive modes of operation. As a result, the DQsignals in diagram 300 are output in synchronism with the CLK signal inboth the modes of operation, as illustrated by the signals for bothmodes crossing at the time T1. In contrast, the signal diagram 302illustrates a situation where the output buffer 108 outputs the DQsignal in synchronism with the CLK signal at the time T1 in thefull-drive mode of operation, but outputs the DQ signal at a differenttime T2 earlier than the time T1 in the reduced-drive mode of operation.In this example, the output buffer 108 has a delay D2′ that is less thanthe delay D2 modeled by the feedback delay line 104 (FIG. 1) in thereduced-drive mode, resulting in the DQ signal being output at theearlier time T2 relative to the CLK signal at the time T1.

[0010] The signal diagram 304 illustrates the third situation where theoutput buffer 108 outputs the DQ signal in synchronism with the CLKsignal at the time T1 in the full-drive mode of operation, but outputsthe DQ signal at a different time T3 later than the time T1 in thereduced-drive mode of operation. In this situation, output offer 108 hasa delay D2′ that is greater than the delay D2 modeled by the feedbackdelay line 104 in the reduced-drive mode, resulting in the DQ signalbeing output at the later time T3 relative to the CLK signal at the timeT1. Thus, FIG. 3 illustrates that in a conventional DDR SDRAM the DQsignals placed on a data bus of the memory device may not be placed onthe data bus in synchronism with the CLK signal when the output buffers108 switch between full-drive and reduced-drive modes of operation. Anaccess time TAC(MIN) and an access time TAC(MAX) are specified for thememory device, and correspond to the maximum time before and after,respectively, the transition of the CLK signal at the time T1 that thetransition of the DQ signal can occur. A conventional memory device maynot satisfy the access times TAC(MIN), TAC(MAX) in both the full- andreduced-drive modes of operation. In the example of FIG. 3, the signaldiagram 302 illustrates a situation where the memory device does notsatisfy the access time TAC(MIN) during the reduced-drive mode, whilethe signal diagram 304 illustrates a situation where the memory devicedoes not satisfy the time TAC(MAX) during the reduced-drive mode.

[0011] There is a need for a outputting data and other signals insynchronism with an external clock signal in memory devices such as DDRSDRAMs that include output buffers that can operate in full-drive andreduced-drive modes of operation.

SUMMARY OF THE INVENTION

[0012] According to one aspect of the present invention, a delay-lockedloop, includes a variable delay line that receives an input clock signaland generates a delayed clock signal responsive to the input clocksignal. The delayed clock signal has a delay relative to the input clocksignal and the variable delay circuit controls the value of the delayresponsive to a delay control signal. A mode delay line receives anoutput drive strength signal and generates a mode delayed clock signalhaving a mode delay relative to the delayed clock signal. The mode delayis a function of the output drive strength signal. A feedback delay linegenerates a feedback clock signal responsive to the mode delayed clocksignal. The feedback clock signal has a model delay relative to the modedelayed clock signal. A comparison circuit receives the input andfeedback clock signals and generates the delay control signal inresponse to the relative phases of these clock signals.

[0013] According to another aspect of the present invention, adelay-locked loop includes a variable delay line adapted to receive aninput clock signal and generate a delayed clock signal responsive to theinput clock signal. The delayed clock signal has a delay relative to theinput clock signal and the variable delay circuit controls the value ofthe delay responsive to a delay control signal. A comparison circuitreceives the input clock signal and generates the delay control signalin response to the relative phases of the delayed and input clocksignals. A mode delay line receives an output drive strength signal andgenerates a mode delayed clock signal having a mode delay relative tothe delayed clock signal. The mode delay is a function of the outputdrive strength signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a functional block diagram of a conventionaldelay-locked loop.

[0015]FIG. 2 is a signal timing diagram illustrating various signalsgenerated during operation of the delay-locked loop of FIG. 1.

[0016]FIG. 3 is a signal timing diagram illustrating the operation ofthe output buffer of FIG. 1 during full-drive and reduced-drive modes ofoperation when the buffer is contained in a DDR SDRAM.

[0017]FIG. 4 is a functional block diagram illustrating a delay-lockedloop for adjusting a delay of a delayed clock signal in response to anoutput buffer operating in either a full-drive or reduced-drive mode ofoperation according to one embodiment of the present invention.

[0018]FIG. 5 is a functional block diagram illustrating a delay-lockedloop for adjusting a mode delay in response to an output bufferoperating in either a full-drive or reduced-drive mode of operationaccording to another embodiment of the present invention.

[0019]FIG. 6 is a signal timing diagram illustrating the operation ofthe delay-locked loop's of FIG. 4 and FIG. 5 in adjusting the delay ofthe delayed clock signal.

[0020]FIG. 7 is a functional block diagram and schematic illustratingone embodiment of the model delay line of FIGS. 4 and 5.

[0021]FIG. 8 is a schematic illustrating another embodiment of the modeldelay line of FIGS. 4 and 5.

[0022]FIG. 9 is a functional block diagram of a DDR SDRAM including thedelay-locked loop of FIG. 4 and/or the delay-locked loop of FIG. 5.

[0023]FIG. 10 is a functional block diagram illustrating a computersystem including the DDR SDRAM of FIG. 9.

DETAILED DESCRIPTION OF THE INVENTION

[0024]FIG. 4 is a functional block diagram illustrating one embodimentof a delay-locked loop 400 that synchronizes an external clock signalCLK signal and a synchronized clock signal CLKSYNC during full- andreduced-drive modes of operation of an output buffer 402. Morespecifically, the delay-locked loop 400 adjusts a variable delay VD of adelayed clock signal CLKDEL in response to the state of an output drivestrength bit DS stored in an extended load mode register 404 to therebycompensate for variations in a delay D2 of the output buffer 402 betweenthe full- and reduced-drive modes of operation, with the state of the DSbit determining the mode of operation of the output buffer, as will nowbe explained in more detail below.

[0025] Although the following discussion describes a delayed-lockedloop, other clock synchronization circuits such as an SMD may also beutilized, as will be appreciated by those skilled in the art. Moreover,any type of integrated circuit that has the need for synchronizinginternal and external clock signals may utilize a clock synchronizationcircuit that embodies aspects of the present invention. In the followingdescription, certain details are set forth to provide a sufficientunderstanding of the invention. It will be clear to one skilled in theart, however, that the invention may be practiced without theseparticular details. In other instances, well-known circuits, controlsignals, timing protocols, and software operations have not been shownin detail or omitted entirely in order to avoid unnecessarily obscuringthe invention.

[0026] In the delay-locked loop 400, the components 406-414 operate inthe same way as previously described for the for the correspondingcomponents in the delay-locked loop 100 of FIG. 1, and thus, for thesake of brevity, the operation of these components will not again bedescribed in detail. The delay-locked loop 400 further includes a modedelay line 416 that generates a mode-delayed clock signal MDCLK inresponse to the CLKDEL signal, and applies the MDCLK signal to thefeedback delay line 414. The mode delay line 416 receives the DS bitfrom the extended load mode register 404, and delays the MDCLK signalrelative to the CLKDEL signal by a mode delay MD having a value that isdetermined by the state of the DS bit. When the DS bit equals a logic 0,the delay MD is approximately zero and the mode delay line 416 outputsthe CLKDEL signal as the MDCLK signal. In contrast, when the DS bitequals a logic 1, the mode delay line 416 outputs the MDCLK signalhaving the delay MD relative to the CLKDEL signal. As will be discussedin more detail below, the delay MD can be either a positive or negativevalue. The state of the DS bit defines the mode of operation of theoutput buffer 402, and when the DS bit equals a logic 0 and a logic 1the output buffer operates in the full-drive and reduced-drive modes,respectively, as will also be explained in more detail below.

[0027] In operation, the delay-locked loop 400 operates in a full-driveand reduced drive mode of operation to synchronize the CLK and CLKSYNCsignals, as will now be explained in more detail. To place thedelay-locked loop 400 in the full-drive mode, the DS bit having a logic0 is stored in the extended load mode register 404. As will beappreciated by those skilled in the art, the extended load mode register404 is in the DDR SDRAM or other integrated circuit containing thedelay-locked loop 400. The manner in which the DS bit is stored in theregister 404 when the delay-locked loop 400 is contained in a DDR SDRAMwill be described in more detail below. When the DS bit is a 0, theoutput buffer 402 has a delay D2 and the mode delay line 416 outputs theCLKDEL signal as the MDCLK signal. In this situation, the mode delayline 416 adds no additional delay and a delay-locked loop 400 operatesas previously described for the delay-locked loop 100 of FIG. 1 tosynchronize the CLK and CLKSYNC signals. Thus, during the full-drivemode the variable delay VD of the variable delay line 408 is adjusteduntil it equals NTCK−(D1+D2), as shown in FIG. 4 and as previouslydescribed for the delay-locked loop 100.

[0028] To place the delay-locked loop 400 in the reduced-drive mode, theDS bit having a logic 1 is stored in the extended load mode register404. When the DS bit is a 1, the output buffer 402 has a delay D2′ andthe mode delay line 416 outputs the MDCLK signal having the delay MDrelative to the CLKDEL signal. In response to the delay MD being addedin the feedback path between the CLKDEL signal and the CLKFB signal, thedelay-locked loop 400 adjusts the variable delay VD of the variabledelay line 408 until the CLKFB and CLKBUF signals are once again locked,which occurs when the variable delay VD of the variable delay line 408equals NTCK−(D1+D2+MD). In the reduced-drive mode, the mode delay line416 introduces the delay MD which, when added to the delay D2 of theoutput buffer 402 for the full-drive mode, equals the delay D2′ of theoutput buffer in the reduced-drive mode. Thus, the variable delay VD ofthe variable delay line 408 equals NTCK−(D1+D2+MD), where D2′=D2+MD. Inthis way, the delay-locked loop 400 adjusts the variable delay VD of theCLKDEL signal to synchronize the CLK and CLKSYNC signals during thereduced-drive mode.

[0029]FIG. 5 is a functional block diagram illustrating anotherembodiment of a delay-locked loop 500 that synchronizes an externalclock signal CLK signal and a synchronized clock signal CLKSYNC duringfull- and reduced-drive modes of operation of an output buffer 502. Morespecifically, the delay-locked loop 500 compensates for variations in adelay D2 of the output buffer 502 between modes by adding a mode delayMD in series with the delay D2 of the output buffer in response to thestate of an output drive strength bit DS stored in an extended load moderegister 504, as will now be explained in more detail below. In thedelay-locked loop 500, the components 502-514 operate in the same way aspreviously described for the corresponding components in thedelay-locked loop 400 of FIG. 4, and thus, for the sake of brevity, theoperation of these components will not again be described in detail.

[0030] Similar to the delay-locked loop 400 of FIG. 4, the delay-lockedloop 500 includes a mode delay line 516 that receives the DS bit fromthe extended load mode register 504, but instead of being coupled in thefeedback path between the CLKDEL and CLKFB signals as in thedelay-locked loop 400, the mode delay line 516 is coupled between theoutput of the variable delay line 508 and the input of the output buffer502. The mode delay line 516 operates in the same way as the mode delayline 416 to generate a mode delayed clock signal MDCLK in response tothe CLKDEL signal, and applies the MDCLK signal to the input of theoutput buffer 502. The mode delay line 516 delays the MDCLK signalrelative to the CLKDEL signal by a mode delay MD having a value that isdetermined by the state of the DS bit from the extended load moderegister 504. When the DS bit equals a logic 0, the delay MD isapproximately zero and the mode delay line 516 outputs the CLKDEL signalas the MDCLK signal. In contrast, when the DS bit equals a logic 1, themode delay line 516 outputs the MDCLK signal having the delay MDrelative to the CLKDEL signal. Once again, the state of the DS bitdefines the mode of operation of the output buffer 502, and when the DSbit equals a logic 0 and a logic 1 the output buffer operates in thefull-drive and reduced-drive modes, respectively.

[0031] In operation, the delay-locked loop 500 operates in a full-driveand reduceddrive mode of operation to synchronize the CLK and CLKSYNCsignals, as will now be explained in more detail. To place thedelay-locked loop 500 in the full-drive mode, the DS bit having a logic0 is stored in the extended load mode register 504. When the DS bit is a0, the output buffer 502 has a delay D2 and the mode delay line 516outputs the CLKDEL signal as the MDCLK signal. In this situation, themode delay line 516 adds no additional delay and a delay-locked loop 500operates as previously described for the delay-locked loop 100 of FIG. 1to synchronize the CLK and CLKSYNC signals. Thus, during the full-drivemode the variable delay VD of the variable delay line 508 is adjusteduntil it equals NTCK−(D1+D2), as shown in FIG. 5 and as previouslydescribed for the delay-locked loop 100.

[0032] To place the delay-locked loop 500 in the reduced-drive mode, theDS bit having a logic 1 is stored in the extended load mode register504. When the DS bit is a 1, the output buffer 502 has a delay D2′ andthe mode delay line 516 outputs the MDCLK signal having the delay MDrelative to the CLKDEL signal. The delay MD results in the MDCLK that isapplied to the output buffer 502 being shifted by the delay MD relativeto the CLKDEL signal. As a result, the delay between the CLKDEL signaland the CLKSYNC signal output from the buffer 502 equals MD+D2′ duringthe reduced-drive mode. The delay MD introduced by the mode delay line516 during the reduced-drive mode has a value so that MD+D2′=D2 tocompensate for the variation in the delay of the output buffer 502.Thus, in the reduced-drive mode, the mode delay line 516 introduces thedelay MD which, when added to the delay D2′ of the output buffer 502,equals the delay D2 for the output buffer in the full-drive mode. Inthis way, the delay-locked loop 500 adjusts the variable delay VD of theCLKDEL signal to NTCK−(D1+D2) and the mode delay line 516 introduces thedelay MD to compensate for variations in the delay of the output buffer502 between the full- and reduced-drive modes. Once again, the value ofthe delay MD introduced by the mode delay line 516 may be positive ornegative.

[0033]FIG. 6 is a signal timing diagram illustrating the operation ofthe delay-locked loops 400 and 500 of FIGS. 4 and 5, respectively, inintroducing the mode delay MD to thereby synchronize the CLK and CLKSYNCsignals during the reduced-drive mode of operation of the output buffers402, 502. In FIG. 6, the CLK signal transitions high at a time the T0,and a signal diagram 600 illustrates that without the addition of themode delay MD, the CLKSYNC signal would transition high at a time T1prior to the timing T0 as indicated by the dotted line 602. In thissituation, the delay D2′ of the output buffer 402, 502 in thereduced-drive mode is less than the delay D2 of the output buffer duringthe full-drive mode, and the CLK and CLKSYNC signals are notsynchronized. The delay-locked loops 400, 500 introduce the mode delayMD to thereby shift the transition of the CLKSYNC signal to the time T0and in synchronism with the CLK signal. The same type of adjustment isillustrated by the signal diagram 604 for the situation where the outputbuffers 402, 502 output data signals DQ in response to be appliedCLKDEL, MDCLK signals. Similarly, signal diagrams 606 and 608 illustratethe operation of the delay-locked loops 400, 500 in introducing the modedelay MD to compensate for the situation where the delay of the outputbuffer 402, 502 in the reduced-drive mode is greater than the delay D2of the output buffer during the full-drive mode. In this situation, themode delay lines 416, 516 at a delay MD to shift the CLKSYNC and DQsignals from a time T2 to the time T0 and in synchronism with the CLKsignal.

[0034] It should be noted that the mode delay MD introduced by the modedelay lines 416, 516 has the same magnitude but different polarities inthe delay-locked loops 400 and 500. For example, in the situationdepicted by the signal diagram 600 in FIG. 6, the mode delay line 516introduces a positive mode delay MD having a value D2−D2′. In contrast,the mode delay line 416 introduces a negative mode delay MD having themagnitude D2−D2′, which causes the CLKFB signal to have a positive phaseshift relative to the CLKBUF signal and thereby causes the phasedetector 410 and delay controller 412 to increase the variable delay VDof the CLKDEL signal until the CLK and CLKSYNC signals are synchronized.In this situation, the delay-locked loop 400 will consume less powerthan the delay-locked loop 500 due to less of the variable delay line408 being utilized relative to the variable delay line 508, as will beappreciated by those skilled in the art. In the situation depicted bythe signal diagrams 606 and 608, the mode delay line 516 introduces anegative the mode delay MD having the value D2−D2′, while the mode delayline 416 introduces a positive mode delay having the same magnitude. Inthis situation, the delay-locked loop 400 consumes more power than thedelay-locked loop 500 due to more of the variable delay line 408 beingutilized relative to the variable delay line 508.

[0035]FIG. 7 is a schematic and a functional block diagram illustratingone embodiment of the mode delay lines 416, 516 in the delay-lockedloops 400, 500 of FIGS. 4 and 5. In the following description, theembodiment depicted in FIG. 7 will be referred to as the mode delay line416 simply for ease of description. In the embodiment of FIG. 7, themode delay line 416 includes a plurality of delay stages 700A-D coupledin series through a plurality of switches SW1-5 between an inputterminal 702 adapted to receive the CLKDEL signal and an output terminal704 on which the MDCLK signal is developed. Each delay stage 700A-D isformed by two series-connected inverters 706. A control circuit 708controls the positions of the switches SW1-5 in response to the state ofthe DS bit and a plurality of control signals 710, which are applied byother circuitry in a DDR SDRAM or other integrated circuit containingthe delay-locked loop 400 (FIG. 4). The control circuit 708 adjusts themagnitude of the mode delay MD in response to the control signals 710 byselectively positioning the switches SW1-5 between the positions 1, 2 asshown.

[0036] The control circuit 708 allows the DDR SDRAM containing thedelay-locked loop 400 and mode delay line 416 to be characterized duringmanufacture and testing to determine the appropriate magnitude andpolarity of the required mode delay MD. Typically, this would be done byloading a logic 1 for the DS bit into the extended load mode register404 and thereby placing the output buffer 402 in the reduced-drive modeof operation. The transitions of the CLKSYNC and DQ signals wouldthereafter be monitored to determine whether the transitions of thesignals comply with the specified access time TAC parameters specifiedfor the memory device. When these transitions are initially monitored,the control circuit 708 initially controls the switches SW1-5 to causethe mode delay MD to have an initial value that may thereafter beincreased or decreased as required. For example, the control circuit 708may initially place the switches SW1-5 in the positions illustrated inFIG. 7 so that the applied CLKDEL signal bypasses the delay stages 700Aand 700B and is applied through the stages 700C and 700D to generate theMDCLK signal. At this point, the mode delay MD has an initial value MDIdetermined by the delay of the delay stages 700C-D. The transitions ofthe CLKSYNC and DQ signals are thereafter monitored and the controlsignals 710 applied to the control circuit 708 which, in turn, positionsthe switches SW1-5 to adjust the initial mode delay MDI as required. Forexample, if the initial mode delay MDI is to be increased, the switchSW3 is moved to position 1 while the switch SW2 is moved to position 2to thereby increase the initial mode MDI by the delay of the delay stage700B. In contrast, if the initial mode delay MDI is to be decreased, theswitch SW3 is moved to position 1 while the switch SW4 is moved toposition 2 to thereby decrease the initial mode delay MDI by the delayof the delay stage 700C.

[0037]FIG. 8 is a schematic illustrating another embodiment of the modedelay lines 416 and 516 of FIGS. 4 and 5 that introduce the mode delayMD having a fixed value. In the embodiment of FIG. 8, the DS bit isapplied through an inverter 800 to alternately activate complementarytransmission gates 802 and 804. When the DS bit is a logic 0, whichdefines the full-drive mode of operation, if the transmission gate 804is activated and applies the CLKDEL signal as the MDCLK signal having anegligible mode delay MD (assuming the delay through the transmissiongate 804 is negligible). In contrast, when the DS bit is a logic 1,which defines the reduced-drive mode of operation, the transmission gate802 is activated and applies the CLKDEL signal through a fixed delaycircuit 806 to generate the MDCLK signal having a fixed mode delay MDrelative to the CLKDEL signal.

[0038]FIG. 9 is a functional block diagram of a memory device 900including the delay-locked loop 400 of FIG. 4 and/or the delay-lockedloop 500 of FIG. 5 to generate the clocks signals CLKDEL or MDCLK toclock data drivers 901, which correspond to the output buffers 402, 502,during full-drive and reduced-drive modes of operation of the datadrivers, as will now be explained in more detail. The data drivers 901output data signals DQ0-DQ31 and a data strobe signal DQS on a data busDATA in synchronism with an applied external clock signal CLK inresponse to the CLKDEL/ MDCLK signal from the delay-locked loop 400/500.The memory device 900 in FIG. 9 is a double-data rate (DDR) synchronousdynamic random access memory (“SDRAM”), although as previously mentionedthe principles described herein are applicable to any memory device thatmay include a delay-locked loop or other clock synchronization circuitfor synchronizing internal and external signals, such as conventionalsynchronous DRAMs (SDRAMs), as well as packetized memory devices likeSLDRAMs and RDRAMs, and are equally applicable to any integrated circuitthat must synchronize internal and external clocking signals.

[0039] The memory device 900 includes an address register 902 thatreceives row, column, and bank addresses over an address bus ADDR, witha memory controller (not shown) typically supplying the addresses. Theaddress register 902 receives a row address and a bank address that areapplied to a row address multiplexer 904 and bank control logic circuit906, respectively. The row address multiplexer 904 applies either therow address received from the address register 902 or a refresh rowaddress from a refresh counter 908 to a plurality of row address latchand decoders 910A-D. The bank control logic 906 activates the rowaddress latch and decoder 910A-D corresponding to either the bankaddress received from the address register 902 or a refresh bank addressfrom the refresh counter 908, and the activated row address latch anddecoder latches and decodes the received row address. In response to thedecoded row address, the activated row address latch and decoder 910A-Dapplies various signals to a corresponding memory bank 912A-D to therebyactivate a row of memory cells corresponding to the decoded row address.Each memory bank 912A-D includes a memory-cell array having a pluralityof memory cells arranged in rows and columns, and the data stored in thememory cells in the activated row is stored in sense amplifiers in thecorresponding memory bank. The row address multiplexer 904 applies therefresh row address from the refresh counter 908 to the decoders 910A-Dand the bank control logic circuit 906 uses the refresh bank addressfrom the refresh counter when the memory device 900 operates in anauto-refresh or self-refresh mode of operation in response to an auto-or self-refresh command being applied to the memory device 900, as willbe appreciated by those skilled in the art.

[0040] A column address is applied on the ADDR bus after the row andbank addresses, and the address register 902 applies the column addressto a column address counter and latch 914 which, in turn, latches thecolumn address and applies the latched column address to a plurality ofcolumn decoders 916A-D. The bank control logic 906 activates the columndecoder 916A-D corresponding to the received bank address, and theactivated column decoder decodes the applied column address. Dependingon the operating mode of the memory device 900, the column addresscounter and latch 914 either directly applies the latched column addressto the decoders 916A-D, or applies a sequence of column addresses to thedecoders starting at the column address provided by the address register902. In response to the column address from the counter and latch 914,the activated column decoder 916A-D applies decode and control signalsto an I/O gating and data masking circuit 918 which, in turn, accessesmemory cells corresponding to the decoded column address in theactivated row of memory cells in the memory bank 912A-D being accessed.

[0041] During data read operations, data being read from the addressedmemory cells is coupled through the I/O gating and data masking circuit918 to a read latch 920. The I/O gating and data masking circuit 918supplies N bits of data to the read latch 920, which then applies twoN/2 bit words to a multiplexer 922. In the embodiment of FIG. 3, thecircuit 918 provides 64 bits to the read latch 920 which, in turn,provides two 32 bits words to the multiplexer 922. The data driver 901sequentially receives the N/2 bit words from the multiplexer 922, andalso receives a data strobe signal DQS from a strobe signal generator926 and the delayed clock signal CLKDEL/MDCLK from the delay-locked loop300/500. The DQS signal is used by an external circuit such as a memorycontroller (not shown) in latching data from the memory device 900during read operations. In response to the delayed clock signal CLKDEL/MDCLK the data driver 901 sequentially outputs the received N/2 bitswords as a corresponding data word DQ, each data word being output insynchronism with a rising or falling edge of a CLK signal that isapplied to clock the memory device 900. The data driver 901 also outputsthe data strobe signal DQS having rising and falling edges insynchronism with rising and falling edges of the CLK signal,respectively. Each data word DQ and the data strobe signal DQScollectively define the data bus DATA. As will be appreciated by thoseskilled in the art, the CLKDEL/MDCLK signal from the delay-locked loop400/500 is a delayed version of the CLK signal, and the delay-lockedloop adjusts the delay of the CLKDEL/MDCLK signal relative to the CLKsignal to ensure that the DQS signal and the DQ words are placed on theDATA bus in synchronism with the CLK signal during both full-drive andreduced-drive modes of operation of the data drivers 901, as previouslydescribed. The DATA bus also includes masking signals DM0-M, which willbe described in more detail below with reference to data writeoperations.

[0042] During data write operations, an external circuit such as amemory controller (not shown) applies N/2 bit data words DQ, the strobesignal DQS, and corresponding data masking signals DM0-X on the data busDATA. A data receiver 928 receives each DQ word and the associated DM0-Xsignals, and applies these signals to input registers 930 that areclocked by the DQS signal. In response to a rising edge of the DQSsignal, the input registers 930 latch a first N/2 bit DQ word and theassociated DM0-X signals, and in response to a falling edge of the DQSsignal the input registers latch the second N/2 bit DQ word andassociated DM0-X signals. The input register 930 provides the twolatched N/2 bit DQ words as an N-bit word to a write FIFO and driver932, which clocks the applied DQ word and DM0-X signals into the writeFIFO and driver in response to the DQS signal. The DQ word is clockedout of the write FIFO and driver 932 in response to the CLK signal, andis applied to the I/O gating and masking circuit 918. The I/O gating andmasking circuit 918 transfers the DQ word to the addressed memory cellsin the accessed bank 912A-D subject to the DM0-X signals, which may beused to selectively mask bits or groups of bits in the DQ words (i.e.,in the write data) being written to the addressed memory cells.

[0043] A control logic and command decoder 934 receives a plurality ofcommand and clocking signals over a control bus CONT, typically from anexternal circuit such as a memory controller (not shown). The commandsignals include a chip select signal CS*, a write enable signal WE*, acolunm address strobe signal CAS*, and a row address strobe signal RAS*,while the clocking signals include a clock enable signal CKE* andcomplementary clock signals CLK, CLK*, with the “*” designating a signalas being active low. The command signals CS*, WE*, CAS*, and RAS* aredriven to values corresponding to a particular command, such as a read,write, or load mode register command. In response to the clock signalsCLK, CLK*, the command decoder 934 latches and decodes an appliedcommand, and generates a sequence of clocking and control signals thatcontrol the components 902-932 to execute the function of the appliedcommand. The clock enable signal CKE enables clocking of the commanddecoder 934 by the clock signals CLK, CLK*. The command decoder 934latches command and address signals at positive edges of the CLK, CLK*signals (i.e., the crossing point of CLK going high and CLK* going low),while the input registers 930 and data drivers 901 transfer data intoand from, respectively, the memory device 900 in response to both edgesof the data strobe signal DQS and thus at double the frequency of theclock signals CLK, CLK*. This is true because the DQS signal has thesame frequency as the CLK, CLK* signals. The memory device 900 isreferred to as a double-data-rate device because the data words DQ beingtransferred to and from the device are transferred at double the rate ofa conventional SDRAM, which transfers data at a rate corresponding tothe frequency of the applied clock signal. The detailed operation of thecontrol logic and command decoder 934 in generating the control andtiming signals is conventional, and thus, for the sake of brevity, willnot be described in more detail.

[0044] The control logic and command decoder 934 also includes a loadmode register, which includes the extended load mode register 404/504previously discussed with reference to FIGS. 4 and 5. An externalcircuit, such as a memory controller or memory tester, applies thecommand signals CS*, WE*, CAS*, and RAS* corresponding to a load moderegister command to control the state of the DS bit contained in theextended load mode register 404/504. Moreover, during characterizationof the memory device 900 in the reduced-drive mode as previouslydiscussed with reference to FIG. 7, the control logic and commanddecoder 934 supplies the control signals 710 to the control circuit 708(see FIG. 7) to adjust the value of the mode delay MD to the requiredvalue.

[0045]FIG. 10 is a block diagram of a computer system 1000 includingcomputer circuitry 1002 including the memory device 900 of FIG. 9.Typically, the computer circuitry 1002 is coupled through address, data,and control buses to the memory device 900 to provide for writing datato and reading data from the memory device. The computer circuitry 1002includes circuitry for performing various computing functions, such asexecuting specific software to perform specific calculations or tasks.In addition, the computer system 1000 includes one or more input devices1004, such as a keyboard or a mouse, coupled to the computer circuitry1002 to allow an operator to interface with the computer system.Typically, the computer system 1000 also includes one or more outputdevices 1006 coupled to the computer circuitry 1002, such as outputdevices typically including a printer and a video terminal. One or moredata storage devices 1008 are also typically coupled to the computercircuitry 1002 to store data or retrieve data from external storagemedia (not shown). Examples of typical storage devices 1008 include hardand floppy disks, tape cassettes, compact disk read-only (CD-ROMs) andcompact disk readwrite (CD-RW) memories, and digital video disks (DVDs).

[0046] It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. For example, many of the components described above may beimplemented using either digital or analog circuitry, or a combinationof both, and also, where appropriate, may be realized through softwareexecuting on suitable processing circuitry. Therefore, the presentinvention is to be limited only by the appended claims.

1. A delay-locked loop, comprising: a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; and a comparison circuit adapted to receive the input clock signal and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the input and feedback clock signals.
 2. The delay-locked loop of claim I wherein the output drive strength signal corresponds to an output drive strength bit stored in a load mode register.
 3. The delay-locked loop of claim I wherein the mode delay line generates a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state.
 4. The delay-locked loop of claim 3 wherein the first logic state of the output drive strength signal corresponds to a full-drive mode of operation of an output buffer adapted to receive the delayed clock signal, and the second logic state of the output drive strength signal corresponds to a reduced-drive mode of operation of the output buffer.
 5. The delay-locked loop of claim 4 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.
 6. The delay-locked loop of claim I wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.
 7. The delay-locked loop of claim 1 wherein the comparison circuit comprises a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.
 8. A delay-locked loop, comprising: a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line and adapted to receive the input clock signal, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.
 9. The delay-locked loop of claim 8 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.
 10. The delay-locked loop of claim 8 wherein the mode delay line generates a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state.
 11. The delay-locked loop of claim 10 wherein the first logic state of the output drive strength signal corresponds to a full-drive mode of operation of an output buffer adapted to receive the mode delayed clock signal, and the second logic state of the output drive strength signal corresponds to a reduced-drive mode of operation of the output buffer.
 12. The delay-locked loop of claim 11 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.
 13. The delay-locked loop of claim 8 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.
 14. The delay-locked loop of claim 8 wherein the comparison circuit comprises: a fixed delay line that generates a feedback clock signal in response to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal; and a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.
 15. A delay-locked loop, comprising: an input buffer adapted to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a mode delay line adapted to receive a output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; a comparison circuit coupled to the input buffer and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the buffered and feedback clock signals; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.
 16. The delay-locked loop of claim 15 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.
 17. The delay-locked loop of claim 15 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.
 18. The delay-locked loop of claim 15 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.
 19. The delay-locked loop of claim 1 wherein the comparison circuit comprises a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.
 20. The delay-locked loop of claim 15 wherein the first and second synchronized output signals correspond to first and second synchronized clock signals having voltage and current characteristics associated with the full- and reduced-drive modes of operation, respectively.
 21. A delay-locked loop, comprising: an input buffer adapted to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal; a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and buffered clock signals; a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state; and an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.
 22. The delay-locked loop of claim 21 wherein the output drive strength signal corresponds to a output drive strength bit stored in a load mode register.
 23. The delay-locked loop of claim 21 wherein the first mode delay comprises a value that is substantially less than a value of the second mode delay.
 24. The delay-locked loop of claim 21 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the mode delay line being operable in the reduced-drive mode to provide the second mode delay having a value equal to the magnitude of the first output delay minus the second output delay.
 25. The delay-locked loop of claim 21 wherein the first and second synchronized output signals correspond to first and second synchronized clock signals having voltage and current characteristics associated with the full- and reduced-drive modes of operation, respectively.
 26. The delay-locked loop of claim 21 wherein the comparison circuit comprises: a fixed delay line that generates a feedback clock signal in response to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal; and a phase detection circuit coupled to receive the feedback clock signal and the input clock signal and operable to develop the delay control signal responsive to the relative phases of the feedback and input clock signals.
 27. A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronization circuit coupled at least to the read/write circuit and adapted to receive an input clock signal, the clock synchronization circuit comprising, a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal that is a function of a delay control signal; an output mode circuit adapted to receive a output drive strength signal and coupled to the variable delay line, the mode circuit operable to adjust the value of the delay control signal to provide a delayed clock signal having a first delay responsive to the output drive strength signal having a first state, and operable to adjust the value of the delay control signal to provide a delayed clock signal having a second delay responsive to the output drive strength signal having a second state; and an output circuit coupled to the variable delay line and the output mode circuit, the output circuit operable in a first output drive strength mode responsive to the output drive strength signal having the first state to generate an output signal responsive to the delayed clock signal having the first delay, and operable in a second output drive strength mode responsive to the output drive strength signal having the second state to generate the output signal responsive to the delayed clock signal having the second delay.
 28. The memory device of claim 27 wherein the memory device comprises a DDR SDRAM and the delayed clock signal is applied to clock an output driver contained in the read/write circuit.
 29. A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a delay-locked loop coupled to at least the read/write circuit and being adapted to receive an input clock signal, the delay-locked loop comprising, a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.
 30. The memory device of claim 29 wherein the memory device comprises a DDR SDRAM and the delayed clock signal is applied to clock an output driver contained in the read/write circuit.
 31. A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronization circuit coupled at least to the read/write circuit and adapted to receive an input clock signal, the clock synchronization circuit comprising, a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal that is a function of a delay control signal; an output mode circuit adapted to receive a output drive strength signal and coupled to the variable delay line, the mode circuit operable to adjust the value of the delay control signal to provide a delayed clock signal having a first delay responsive to the output drive strength signal having a first state, and operable to adjust the value of the delay control signal to provide a delayed clock signal having a second delay responsive to the output drive strength signal having a second state; and an output circuit coupled to the variable delay line and the output mode circuit, the output circuit operable in a first output drive strength mode responsive to the output drive strength signal having the first state to generate an output signal responsive to the delayed clock signal having the first delay, and operable in a second output drive strength mode responsive to the output drive strength signal having the second state to generate the output signal responsive to the delayed clock signal having the second delay.
 32. The memory device of claim 31 wherein the memory device comprises a DDR SDRAM and the delayed clock signal is applied to clock an output driver contained in the read/write circuit.
 33. A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a delay-locked loop coupled to at least the read/write circuit and being adapted to receive an input clock signal, the delay-locked loop comprising, a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals; and a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.
 34. The memory device of claim 33 wherein the memory device comprises a DDR SDRAM and the delayed clock signal is applied to clock an output driver contained in the read/write circuit.
 35. A method for adjusting a timing offset between data signals and an applied clock signal, the method comprising: generating a delayed clock signal having a delay relative to the applied clock signal; monitoring a state of an output drive strength bit, the bit having a plurality of states and each state corresponding to a drive-strength mode of the data signals; adjusting the delay of the delayed clock signal in response to the detected state of the output drive strength bit; and outputting the data signals having a timing offset relative to the clock signal, the offset being determined by the delay of the delayed clock signal.
 36. The method of claim 35 wherein the timing offset between the applied clock signal has a value that is substantially less than a period of the applied clock signal.
 37. A method of adjusting a delay of a delayed clock signal relative to an applied clock signal in a delay-locked loop, the method comprising: generating the delayed clock signal having a delay relative to the applied clock signal; delaying the delayed clock signal by a feedback delay to generate a feedback clock signal; detecting a phase difference between the delayed clock signal and the feedback clock signal; adjusting the delay of the delayed clock signal in response to the detected phase difference; detecting a state of an output drive strength bit, the bit having a plurality of states and each state corresponding to a drive-strength mode of the data signals; and adjusting the feedback delay in response to the detected state of the output drive strength bit.
 38. The method of claim 37 wherein the output drive strength bit has two states corresponding to a full-drive and reduced-drive modes of the data signals.
 39. The method of claim 37 wherein generating the delayed clock signal comprises clocking data signals in response to the delayed clock signal.
 40. A method of adjusting a delay of a delayed clock signal relative to an applied clock signal in a delay-locked loop, the method comprising: generating the delayed clock signal having a delay relative to the applied clock signal; detecting a phase difference between the delayed clock signal and the applied clock signal; adjusting the delay of the delayed clock signal in response to the detected phase difference; generating a synchronized clock signal in response to the delayed clock signal, the synchronized clock signal having a delay relative to the delayed clock signal; detecting a state of an output drive strength bit, the bit having a plurality of states and each state corresponding to a drive-strength mode of the data signals; and adjusting the delay of the synchronized clock signal in response to the detected state of the output drive strength bit.
 41. The method of claim 37 wherein the output drive strength bit has two states corresponding to a full-drive and reduced-drive modes of the data signals.
 42. The method of claim 37 wherein generating the synchronized clock signal comprises clocking data signals in response to the delayed clock signal.
 43. A clock synchronization circuit, comprising: a variable delay line adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal that is a function of a delay control signal; an output mode circuit adapted to receive a output drive strength signal and coupled to the variable delay line, the mode circuit operable to adjust the value of the delay control signal to provide a delayed clock signal having a first delay responsive to the output drive strength signal having a first state, and operable to adjust the value of the delay control signal to provide a delayed clock signal having a second delay responsive to the output drive strength signal having a second state; and an output circuit coupled to the variable delay line and the output mode circuit, the output circuit operable in a first output drive strength mode responsive to the output drive strength signal having the first state to generate an output signal responsive to the delayed clock signal having the first delay, and operable in a second output drive strength mode responsive to the output drive strength signal having the second state to generate the output signal responsive to the delayed clock signal having the second delay.
 44. The clock synchronization circuit of claim 43 wherein the clock synchronization circuit comprises a delay-locked loop and the variable delay line comprises a variable delay line circuit coupled to a feedback delay line, and a comparison circuit coupled to the variable delay line circuit and the feedback delay line.
 45. The clock synchronization circuit of claim 43 wherein the output circuit comprises an output buffer and the first output drive strength corresponds to a full-drive mode of operation of the output buffer and the second output drive strength corresponds to a reduced-drive mode of operation of the output buffer.
 46. The clock synchronization circuit of claim 45 wherein the output buffer has a first output delay when operating in the full-drive mode and a second output delay when operating in the reduced-drive mode, the output mode circuit being operable in the reduced-drive mode to adjust the value of the delay control signal to provide a delayed clock signal having a delay equal to the magnitude of the first output delay minus the second output delay.
 47. The clock synchronization circuit of claim 43 wherein the first delay comprises a value that is substantially less than a value of the second delay.
 48. The clock synchronization circuit of claim 43 wherein the output mode circuit comprises a load mode register and the output drive strength signal corresponds to a output drive strength stored in the register.
 49. The memory device of claim 27 wherein the clock synchronization circuit comprises a delay-locked loop and the variable delay line comprises a variable delay line circuit coupled to a feedback delay line, and a comparison circuit coupled to the variable delay line circuit and the feedback delay line.
 50. The computer system of claim 31 wherein the clock synchronization circuit comprises a delay-locked loop and the variable delay line comprises a variable delay line circuit coupled to a feedback delay line, and a comparison circuit coupled to the variable delay line circuit and the feedback delay line. 